1. Field of the Invention
The present invention relates to a semiconductor device.
2. Description of the Related Art
Conventionally, there has been known a semiconductor device where an active element part and a gate pad part are defined on a semiconductor substrate formed by laminating a drain layer (low resistance semiconductor layer) and a drift layer to each other (see FIG. 23 of JP-A-2005-150348 (patent literature 1), for example). FIG. 32A and FIG. 32B are views for explaining a conventional semiconductor device 800. FIG. 32A is a plan view showing an essential part of the semiconductor device 800, and FIG. 32B is a cross-sectional view taken along a line X-X in FIG. 32A.
As shown in FIG. 32A and FIG. 32B, the conventional semiconductor device 800 is a semiconductor device provided with an active element part and a gate pad part defined on a semiconductor substrate which is formed by laminating an n+ drain layer 51 and an n− drift layer 52 to each other. As shown in FIG. 32B, the active element part includes: the n+ drain layer 51; the n− drift layer 52; p base regions 53 formed on a surface of the n− drift layer 52; n+ source regions 54 formed on surfaces of the p base regions 53; gate electrodes 57 formed on the p base regions 53 sandwiched between the n+ source regions 54 and the n− drift layer 52 with gate insulation films 56 interposed therebetween; and source electrodes 61 formed in contact with surfaces of the n+ source regions 54 and the p base regions 53 in a state where the source electrodes 61 are insulated from the gate electrodes 57 with interlayer insulation films 58 interposed therebetween.
On the other hand, as shown in FIG. 32B, the gate pad part includes: the n+ drain layer 51, the n− drift layer 52; a conductor 73 formed of a poly-silicon film formed above the n− drift layer 52 over the whole area of the gate pad part with an interlayer insulation film 72 interposed therebetween; a gate pad electrode 62 formed on the conductor 73; and a p region 71 formed on the surface of the n− drift layer 52 over the whole area of the gate pad part. In FIG. 32A and FIG. 32B, symbol 55 indicates a p+ well region, symbol 59 indicates a source contact hole, symbol 60 indicates a drain electrode, symbol 70 indicates a poly-silicon film, and symbol 74 indicates a p region contact hole.
In the conventional semiconductor device 800, in the gate pad part, the p region 71 is formed on the surface of the n− drift layer 52 over the whole area of the gate pad part. Accordingly, at the time of applying a reverse bias voltage, a depletion layer in the n− drift layer 52 extends toward the n+ drain layer 51 over the whole area of the gate pad part thus providing a semiconductor device having a high breakdown strength.